A researcher at the Indian Institute of Technology (IIT) Delhi has designed a device for high-density magnetic memory,in collaboration with the National University of Singapore(NUS). The proposed device may help reduce frequent charging of wireless electronic devices such as mobile phones and other Internet of Thing (IoT) based devices.

The main memory, i.e., the Random-access memory (RAM) is most commonly used in modern computer architecture. These are SRAMs and DRAMs, which are based on CMOS technology. They are fast but volatile and require a constant supply of power, which consumes lots of energy. But, if these could be made non-volatile, then computing could be made more energy-efficient.

Spintronics memories like spin-transfer torque magneto-resistive RAM (STT-MRAM) and spin-orbit torque magneto-resistive RAM (SOT-MRAM) are inherently non-volatile. They consume no power at standby. Also, their operation speeds are comparable to RAMs. Hence, these spintronics memories are the most potential candidates for replacing current electronic RAMs, says IIT Delhi statement.

SOT-MRAMs are better than STT-MRAM in terms of reliability and writing speed but lags in achieving high integration density. This is because, unlike STT-MRAM, which is a two-terminal device and needs one transistor for reading and writing operation, the SOT-MRAMs require two transistors each for reading and writing. Thus SOT-MRAM requires a larger area per bit as compared to STT-MRAM, as shown in figure-1.

Also, SOT-MRAM is less prone to breakdown due to separate read and write paths, this is absent in STT-MRAMs. Hence, SOT-MRAM is the preferred choice among the research community however significant work is required to increase their areal density.

In a collaborative work between Prof. Rahul Mishra from the Centre for Applied Research in Electronics (CARE), IIT Delhi,and Prof. Hyunsoo Yang from the National University of Singapore(NUS) a possible solution for achieving higher integration density in SOT-MRAMs was proposed and experimentally demonstrated.

Prof. Rahul Mishra, CARE, IIT Delhi said, “We demonstrated a shared write channel based multibit SOT cell scheme, which reduces the number of transistors required per bit. This cell design requires half the area compared to conventional SOT MRAM, thus almost doubles the area efficiency of the memory chip”.

To make the above design feasible, the team designed a magnetic memory device, which can be programmed by the application of gate voltage. The gate voltage was used to migrate oxygen ions in the device, which resulted in modulation of the spin current polarity as shown in Figure 3. Thus, cells can now be written individually, and hence they obtained a full-fledged, working area-efficient SOT memory. The work was published in Physical Review appliedjournal.

Prof. Mishra further said, “The results of this work could eventually help to develop low power electronic devices.The frequent charging of wireless electronic devices such as mobile phones, IoT devices, etc would be significantly reduced with the proposed device. It would be especially useful for industrial applications where sensors are put in locations, which are not easy to access. Low power and high-density memory devices would not only help reduce global energy footprint but the saved energy can also be used for extra computational tasks”.

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Keywords: power, computing, memory, data processing, CPU, Indian Institute of Technology, IIT Delhi, National University of Singapore,NUS, magnetic memory, wireless devices, mobile phones, Internet of Thing, IoT devices

DrAmitaRawat and Prof UdayanGanguly from the Department of Electrical Engineering, Indian Institute of Technology, Bombay (IIT Bombay), in collaboration with researchers from IMEC, Leuven, Belgium, have experimentally validated their previously proposed method to estimate the change in performance of an electronic circuit caused by manufacturing variations. This is the first time that the experimental validation of variations predicted using physics-based modeling has been reported. The predictions can be integrated with circuit design software, thus making it possible to design better-performing circuits. This work was partially funded by the Indian Institute of Technology Nano Fabrication Lab (IITBNF Lab), the Ministry of Human Resource Development (MHRD), and the Department of Science and Technology (DST).

Patterns are drawn using UV light on semiconductor chips to mark the channel, gate, interconnects, and other circuit components. Patterns with lines and spaces smaller than 10 nanometer tend to have fluctuations of about a nanometer. It is also challenging to place dopant atoms perfectly. The gate metal has nanoscale crystals that are not oriented uniformly in the same direction leading to different atomic interfaces between metal crystal and gate insulator. These local physical variations can significantly affect the electrical properties of the transistor. “For example, the variation in how metal is deposited affects the value of the gate voltage at which the transistor starts conducting current,” explains Dr Rawat, the lead author of the study.

As the building blocks of electronic circuits approach the atomic scale, the physical variations become substantial compared to the component dimensions. In commercially-used design and simulation softwares, circuit performance is inexactly evaluated based on simple variation in electrical properties of the transistor that is increasingly inaccurate as transistors shrink. “We provide process specific physics-based estimates of the electrical variation. It enables a more accurate evaluation of the circuit performance,” says Dr Rawat. “The designers can also get an idea of how the variation will alter if they change from one manufacturing process to another,” she adds.

To find the influence of the physical variations on the circuit performance, engineers first need to evaluate its effect on the transistor’s electrical properties. Currently, computational methods are used to study the structures of a few hundreds of transistors to find variations in electrical properties. With hours of costly simulations needed to calculate each transistor’s parameters, the process is computationally expensive and time-consuming. “Also, this method does not provide a simple, intuitive model connecting the structural variations to electrical variations of the transistors, necessary for the circuit designers,” comments Prof Ganguly.

“Our team developed the theoretical modelling of variability over nine years and three PhD theses. The journey is chronicled in a magazine article in IEEE Nanotechnology Magazine. Now our work has reached the experimental validation phase,” says Prof Ganguly.

The researchers created a mathematical model that accurately predicts variations in the transistor electrical properties based on the changes in the physical parameters, such as fluctuations of the pattern lines or metal nanocrystal orientation. The same model works for any manufacturing process. They used this transistor variation data to create a ‘variabilityaware’ transistor model to be used in a commercial design and simulation software. Thus circuits designed using this model capture the actual variability due to the manufacturing process, and designers can get an accurate estimation of the circuit performance. “The beauty of our platform is that the circuit performance prediction can be made available commercially, without significantly adding to the cost,” comments Dr Rawat.

“In addition to making it easier to design better-performing circuits, the proposed method can also provide feedback to the foundry team for improving their processes,” says Dr Rawat. The process designer can determine which process dependent inputs give the desired physical variability parameters. “It is like building a bridge between the circuit designers and the process team.”

In the current study, the researchers used their model to predict the physical variations for the 14nm technology process. They compared these values with the experimentally measured physical variations and found them to match well. They also estimated the variations in electrical properties of the transistor, and these agreed with the experimentally measured variations of a cluster of 250 transistors made with the 14nm technology. The worst and best case errors were within acceptable limits. “Such elaborate experimental validation has not been reported earlier,” remarks Dr Rawat.

The researchers plan to provide this framework as a technology package to be plugged into the circuit design software. “We need to collaborate with foundries to access the latest data of manufacturing processes they use. We can create the process-specific package and get it validated from the foundry. It can evolve into an industry standard,” said DrRawat.

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Keywords: circuit performance, IIT Bombay, circuit design, software, IITBNF Lab, MHRD, Department of Science and Technology, DST.